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DISCRETE SEMICONDUCTORS
DATA SHEET
BF1211; BF1211R; BF1211WR N-channel dual-gate MOS-FETs
Product specification 2003 Dec 16
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
FEATURES * Short channel transistor with high forward transfer admittance to input capacitance ratio * Low noise gain controlled amplifier * Excellent low frequency noise performance * Partly internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization. APPLICATIONS * Gain controlled low noise VHF and UHF amplifiers for 5 V digital and analog television tuner applications.
BF1211; BF1211R; BF1211WR
PINNING PIN 1 2 3 4 drain gate 2 gate 1 DESCRIPTION source
handbook, 2 columns 4
3
1
2
MSB014
DESCRIPTION Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1211, BF1211R and BF1211WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively.
Top view BF1211 marking code: LFp
Fig.1
Simplified outline (SOT143B).
handbook, 2 columns 3
4
handbook, halfpage
3
4
2 Top view BF1211R marking code: LHp
1 2
MSB035
1
MSB842
Top view BF1211WR marking code: MK
Fig.2
Simplified outline (SOT143R).
Fig.3
Simplified outline (SOT343R).
QUICK REFERENCE DATA SYMBOL VDS ID Ptot yfs Cig1-ss Crss F Xmod Tj PARAMETER drain-source voltage drain current total power dissipation forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure cross-modulation junction temperature 2 f = 1 MHz f = 400 MHz input level for k = 1% at 40 dB AGC CONDITIONS - - - 25 - - - 100 - MIN. - - - 30 2.1 15 0.9 105 - TYP. 6 30 180 40 2.6 30 1.6 - 150 MAX. UNIT V mA mW mS pF fF dB dBV C
2003 Dec 16
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1211; BF1211R; BF1211WR
CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME BF1211 BF1211R BF1211WR - - - DESCRIPTION plastic surface mounted package; 4 leads plastic surface mounted package; reverse pinning; 4 leads plastic surface mounted package; reverse pinning; 4 leads VERSION SOT143B SOT143R SOT343R
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDS ID IG1 IG2 Ptot PARAMETER drain-source voltage drain current (DC) gate 1 current gate 2 current total power dissipation BF1211; BF1211R BF1211WR Tstg Tj Note 1. Ts is the temperature of the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL Rth(j-s) BF1211; BF1211R BF1211WR PARAMETER thermal resistance from junction to soldering point 185 155 K/W K/W VALUE UNIT storage temperature junction temperature Ts 116 C; note 1 Ts 122 C; note 1 - - -65 - 180 180 +150 150 mW mW C C CONDITIONS - - - - MIN. 6 30 10 10 MAX. V mA mA mA UNIT
2003 Dec 16
3
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1211; BF1211R; BF1211WR
handbook, halfpage
250
MDB828
Ptot (mW)
200
150
(2)
(1)
100
50
0 0 50 100 150 Ts (C) 200
(1) BF1211WR. (2) BF1211; BF1211R.
Fig.4 Power derating curve.
STATIC CHARACTERISTICS Tj = 25 C unless otherwise specified. SYMBOL V(BR)DSS PARAMETER drain-source breakdown voltage CONDITIONS VG1-S = VG2-S = 0 V; ID = 10 A VG2-S = VDS = 0 V; IG1-S = 10 mA VG1-S = VDS = 0 V; IG2-S = 10 mA VG2-S = VDS = 0 V; IS-G1 = 10 mA VG1-S = VDS = 0 V; IS-G2 = 10 mA VG2-S = 4 V; VDS = 5 V; ID = 100 A VG1-S = 5 V; VDS = 5 V; ID = 100 A VG2-S = 4 V; VDS = 5 V; RG1 = 75 k; note 1 VG2-S = VDS = 0 V; VG1-S = 5 V VG1-S = VDS = 0 V; VG2-S = 4 V MIN. 6 6 6 0.5 0.5 0.3 0.35 11 - - MAX. - 10 10 1.5 1.5 1 1 19 50 20 UNIT V V V V V V V mA nA nA
V(BR)G1-SS gate 1-source breakdown voltage V(BR)G2-SS gate 2-source breakdown voltage V(F)S-G1 V(F)S-G2 VG1-S(th) VG2-S(th) IDSX IG1-S IG2-S Note 1. RG1 connects G1 to VGG = 5 V. forward source-gate 1 voltage forward source-gate 2 voltage gate 1-source threshold voltage gate 2-source threshold voltage drain-source current gate 1 cut-off current gate 2 cut-off current
2003 Dec 16
4
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1211; BF1211R; BF1211WR
DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 15 mA; unless otherwise specified. SYMBOL yfs Cig1-ss Cig2-ss Coss Crss F PARAMETER forward transfer admittance input capacitance at gate 1 input capacitance at gate 2 output capacitance noise figure f = 1 MHz f = 1 MHz f = 1 MHz f = 11 MHz; GS = 20 mS; BS = 0 f = 400 MHz; YS = YS (opt) f = 800 MHz; YS = YS (opt) Gtr power gain f = 200 MHz; GS = 2 mS; BS = BS (opt); GL = 0.5 mS; BL = BL (opt) f = 400 MHz; GS = 2 mS; BS = BS (opt); GL = 1 mS; BL = BL (opt) f = 800 MHz; GS = 3.3 mS; BS = BS (opt); GL = 1 mS; BL = BL (opt) Xmod cross-modulation input level for k = 1%; fw = 50 MHz; funw = 60 MHz; note 1 at 0 dB AGC at 10 dB AGC at 40 dB AGC Note 1. Measured in test circuit Fig.21. 90 - 100 - 92 105 - - - dBV dBV dBV CONDITIONS pulsed; Tj = 25 C MIN. 25 - - - - - - - - - - TYP. 30 2.1 1.1 0.9 15 3.5 0.9 1.3 34 29 24 MAX. 40 2.6 - - 30 - 1.6 2 - - - UNIT mS pF pF pF fF dB dB dB dB dB dB
reverse transfer capacitance f = 1 MHz
2003 Dec 16
5
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1211; BF1211R; BF1211WR
handbook, halfpage
25
MDB829
handbook, halfpage
(1) (2) (3) (4)
24
MDB830
(1)
ID
(mA) 20
ID (mA)
(5)
(2)
16
15
(6)
(3) (4) (5) (6) (7)
10
8
5
(7)
(8)
0 0 0.5 1 1.5 2.5 2 VG1-S (V)
0 0 2 4 VDS (V) 6
VDS = 5 V; Tj = 25 C. (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V.
VG2-S = 4 V; Tj = 25 C. (1) VG1-S = 1.5 V. (2) VG1-S = 1.4 V. (3) VG1-S = 1.3 V. (4) VG1-S = 1.2 V. (5) VG1-S = 1.1 V. (6) VG1-S = 1 V. (7) VG1-S = 0.9 V. (8) VG1-S = 0.8 V.
Fig.5 Transfer characteristics; typical values.
Fig.6 Output characteristics; typical values.
handbook, halfpage
100
MDB831
IG1 (A)
(1) (2) (3) (4)
handbook, halfpage
40
MDB832
yfs (mS) 30
(1) (2)
80
(3)
60
20
(5)
40
(6) (5) (4)
10
20
(6)
(7)
0 0 0.5 1 1.5 VG1-S (V)
VDS = 5 V; Tj = 25 C. (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V.
0
2
0
6
12
18
24 30 ID (mA)
VDS = 5 V; Tj = 25 C. (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V.
Fig.7
Gate 1 current as a function of gate 1 voltage; typical values.
Fig.8
Forward transfer admittance as a function of drain current; typical values.
2003 Dec 16
6
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1211; BF1211R; BF1211WR
handbook, halfpage
20
MDB833
handbook, halfpage
16
MDB834
ID (mA) 16
ID (mA) 12
12 8 8 4 4
0 0 10 20 30 40 50 IG1(A)
0 0 1 2 3 4 5 VGG (V)
VDS = 5 V; VG2-S = 4 V. Tj = 25 C.
VDS = 5 V; VG2-S = 4 V; Tj = 25 C. RG1 = 75 k (connected to VGG); see Fig.21.
Fig.9
Drain current as a function of gate 1 current; typical values.
Fig.10 Drain current as a function of gate 1 supply voltage (VGG); typical values.
handbook, halfpage
20
MDB835
ID
handbook, halfpage
(1) (2) (3) (4) (5) (6) (7)
20
MDB836
(mA) 16
ID (mA)
16
(1) (2) (3)
12
12
(4) (5)
8
8
4
4
0 0 2 4 6 VGG = VDS (V)
0 0 2 4 VG2-S (V) 6
VG2-S = 4 V; Tj = 25 C; RG1 connected to VGG; see Fig.21. (1) RG1 = 47 k. (2) RG1 = 56 k. (3) RG1 = 68 k. (4) RG1 = 75 k. (5) RG1 = 82 k. (6) RG1 = 100 k. (7) RG1 = 120 k.
VDS = 5 V; Tj = 25 C; RG1 = 75 k (connected to VGG); see Fig.21. (1) VGG = 5 V. (2) VGG = 4.5 V. (3) VGG = 4 V. (4) VGG = 3.5 V. (5) VGG = 3 V.
Fig.11 Drain current as a function of gate 1 (VGG) and drain supply voltage; typical values.
Fig.12 Drain current as a function of gate 2 voltage; typical values.
2003 Dec 16
7
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1211; BF1211R; BF1211WR
handbook, halfpage
50
MDB837
gain handbook, halfpage
(1) (2) (3)
0
MDB838
IG1 (A)
40
reduction (dB) -10 -20 -30
30
(4) (5)
20 -40 10 -50 -60 0 2 4 VG2-S (V) 6
0
0
1
2
3 VAGC (V)
4
VDS = 5 V; Tj = 25 C; RG1 = 75 k (connected to VGG); see Fig.21. (1) VGG = 5 V. (2) VGG = 4.5 V. (3) VGG = 4 V. (4) VGG = 3.5 V. (5) VGG = 3 V.
VDS = 5 V; VGG = 5 V; RG1 = 75 k (connected to VGG); see Fig.21; f = 50 MHz; Tamb = 25 C.
Fig.13 Gate 1 current as a function of gate 2 voltage; typical values.
Fig.14 Typical gain reduction as a function of AGC voltage.
handbook, halfpage
120
MDB839
handbook, halfpage
20
MDB840
Vunw (dBV) 110
ID (mA)
16
12 100 8 90 4
80 0 10 20 30 40 50 gain reduction (dB)
0 0 10 20 30 40 50 gain reduction (dB)
VDS = 5 V; VGG = 5 V; RG1 = 75 k (connected to VGG); see Fig.21; f = 50 MHz; funw = 60 MHz; Tamb = 25 C.
VDS = 5 V; VGG = 5 V; RG1 = 75 k (connected to VGG); see Fig.21; f = 50 MHz; Tamb = 25 C.
Fig.15 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values.
Fig.16 Drain current as a function of gain reduction; typical values.
2003 Dec 16
8
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1211; BF1211R; BF1211WR
102 handbook, halfpage yis (mS)
MDB841
103 handbook, halfpage |yrs| (S) 102 rs
MDB842
-103 rs (deg) -102
10
bis 1 10 |yrs| -10
gis 10-1 10 102 103 1 10 102 103 -1
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C.
VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C.
Fig.17 Input admittance as a function of frequency; typical values.
Fig.18 Reverse transfer admittance and phase as a function of frequency; typical values.
102 handbook, halfpage |yfs| (mS) |yfs|
MDB843
-102 fs (deg)
handbook, halfpage
10
MDB844
yos (mS) bos 1
10 fs
-10 gos
10-1
1 10
102
f (MHz)
103
-1
10-2 10
102
f (MHz)
103
VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C.
VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C.
Fig.19 Forward transfer admittance and phase as functions of frequency; typical values.
Fig.20 Output admittance as a function of frequency; typical values.
2003 Dec 16
9
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1211; BF1211R; BF1211WR
handbook, full pagewidth
VAGC R1 10 k
C1 4.7 nF C3 4.7 nF
C2 RGEN 50 VI R2 50 4.7 nF RG1
DUT
2.2 H
C4 4.7 nF
L1
RL 50
VGG
VDS
MGS315
Fig.21 Cross-modulation test set-up.
Table 1 f (MHz) 50 100 200 300 400 500 600 700 800 900 1000 Table 2
Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C s11 MAGNITUDE (ratio) 0.987 0.985 0.979 0.965 0.949 0.929 0.904 0.876 0.846 0.816 0.791 ANGLE (deg) -3.86 -7.73 -15.25 -22.84 -30.15 -30.25 -44.24 -51.16 -58.16 -65.15 -72.22 s21 MAGNITUDE (ratio) 2.928 2.921 2.807 2.846 2.784 2.704 2.639 2.558 2.486 2.402 2.315 ANGLE (deg) 175.8 171.6 163.2 155.0 146.7 138.9 130.9 123.0 115.1 107.2 99.9 s12 MAGNITUDE (ratio) 0.0005 0.0010 0.0015 0.0028 0.0034 0.0037 0.0040 0.0039 0.0037 0.0032 0.0028 ANGLE (deg) 89.3 86.9 91.1 77.4 74.0 71.4 69.6 69.0 70.0 74.5 87.1 s22 MAGNITUDE (ratio) 0.993 0.993 0.993 0.988 0.985 0.981 0.976 0.971 0.965 0.960 0.956 ANGLE (deg) -1.58 -3.14 -6.31 -9.41 -12.48 -15.54 -18.59 -21.65 -24.27 -27.79 -30.94
Noise data: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C f (MHz) 400 800 Fmin (dB) 0.9 1.3 opt (ratio) 0.693 0.707 (deg) 16.75 37.33 Rn () 29.85 29.90
2003 Dec 16
10
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
PACKAGE OUTLINES
BF1211; BF1211R; BF1211WR
Plastic surface mounted package; 4 leads
SOT143B
D
B
E
A
X
y vMA HE
e bp wM B
4
3
Q
A
A1 c
1
b1 e1
2
Lp detail X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.45 0.15 Q 0.55 0.45 v 0.2 w 0.1 y 0.1
OUTLINE VERSION SOT143B
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 97-02-28
2003 Dec 16
11
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1211; BF1211R; BF1211WR
Plastic surface mounted package; reverse pinning; 4 leads
SOT143R
D
B
E
A
X
y vMA HE
e bp wM B
3
4
Q
A
A1 c
2
b1 e1
1
Lp detail X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.55 0.25 Q 0.45 0.25 v 0.2 w 0.1 y 0.1
OUTLINE VERSION SOT143R
REFERENCES IEC JEDEC EIAJ SC-61B
EUROPEAN PROJECTION
ISSUE DATE 97-03-10 99-09-13
2003 Dec 16
12
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1211; BF1211R; BF1211WR
Plastic surface mounted package; reverse pinning; 4 leads
SOT343R
D
B
E
A
X
y
HE e
vMA
3
4
Q
A A1 c
2
wM B bp e1 b1
1
Lp detail X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.4 0.3 b1 0.7 0.5 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 1.15 HE 2.2 2.0 Lp 0.45 0.15 Q 0.23 0.13 v 0.2 w 0.2 y 0.1
OUTLINE VERSION SOT343R
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 97-05-21
2003 Dec 16
13
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development
BF1211; BF1211R; BF1211WR
DEFINITION This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 Dec 16
14
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R77/01/pp15
Date of release: 2003
Dec 16
Document order number:
9397 750 12003

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